Overclocking, by increasing voltages and speeds, alters the optimization of the circuits. Increasing voltage changes the impedance of the circuit and the amount of noise that is present. The consequence of this is an increase of overshoot, ringback and settling time. This results in both an improper representation of the data and an increased flight time necessitating the need for a wider timing window. Increasing the speed requires corresponding tighter timing windows. So voltage and speed are a compromise as what satisfies one is detrimental to the other.

Another issue that most users are unaware of is the relationship between VCORE and VTT. To reduce the amount of ringing at the driver, Intel has added a weak pull-up device to the output buffer as mentioned above. This device turns on at the beginning of a low-to-high signal transition, substantially reducing the impedance mismatch between the output buffer and the transmission line. As a result, the amount of overshoot and ringback is significantly reduced. The source terminal of the pull-up device is connected to the core voltage supply. This causes the logic high voltage to rise above the GTL termination voltage for one cycle. After one bus cycle, the pull-up device is turned-off and the output will stabilize at VTT if the output remains in the logic high state. But when we raise VTT above VCORE we have effectively removed the pull-up device from the circuit.

As has been stated above the high level output is VTT. The low level output is ground (0.00 volts) An output signal that extends into the area between VOL(max) and VIL(min) or VTT(min) and VIH(max) can result in the input voltage not being read correctly.

The receiver side has similar constraints. The low level input must be kept between 0.00 volts and VIL(max). The high level input has a range of VIH(min) and VTT. An input voltage level that crosses either VIL(max) or VIL(min) renders the receiver incapable of determining if the signal is a logic high or low.



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